1. Field of the Invention
The present invention relates to simulation of integrated circuits and in particular to selectively applying Newton-Raphson iterations to specific devices or circuit blocks based on their linearity values.
2. Related Art
As IC technology continues to shrink to 90 nm and below, total power consumption has become one of the most important concerns in chip designs. Known techniques such as power gating, voltage scaling, and variable threshold CMOS have been adopted to reduce standby leakage current and dynamic power dissipation. However, such techniques pose a significant challenge to both pre-layout and post-layout full chip verification due to the extremely large size of the matrices of the nodal analysis equation sets required for simulation.
For example, SPICE is a well-known general-purpose circuit simulation program developed by the University of California at Berkeley. SPICE can simulate circuits including, for example, resistors, capacitors, inductors, voltage sources, current sources, transmission lines, and common semiconductor devices. Fast-SPICE simulators use various algorithms to improve performance over traditional SPICE simulators. Notably, both SPICE and Fast-SPICE use LU (lower-upper) decompositions of matrices for nodal analysis, see e.g. U.S. Pat. No. 7,555,416, which issued on Jun. 30, 2009. Unfortunately, LU decompositions have significant limitations with respect to large-scale circuits.
FIG. 1 is an exemplary technique 100 for the transient analysis of an electronic circuit simulator, which consists of a Newton-Raphson loop 110 and a time-driven loop 120. Step 101 begins by determining model evaluation for a specific integrated circuit design, and initiating simulation based on the unit of the model at time t. Step 102 can solve for an equivalent resistive network numerically. In one embodiment, this network can be represented by linear equations according to a Modified Nodal Analysis (MNA) equation:GVnk+1=I where “G” is a Jacobian matrix that holds conductance values, “V” is a vector that holds voltage change values, “k” is an integer iteration designation starting at zero, “n” is a time stamp, and “I” is a vector that holds current values.
Step 103 determines whether k is greater than or equal to “1”. If k=0 (i.e. before a traversal of loop 110), then step 106 increments k by one and returns to step 101. Generally, any iteration (i.e. a traversal of loop 110) after k=1 is termed a Newton-Raphson iteration. If k≧1, then step 104 determines whether convergence is achieved. If not, then step 106 once again increments k by one and returns to step 101. In this manner, successively better approximations are found to solve the MNA equations. Thus, Newton-Raphson iterations of loop 110 are repeated until convergence is reached in step 104. If convergence is achieved, then step 105 determines whether time t is greater than or equal to a specified total simulation period T (either by user or system default).
If time t is less than simulation period T, then step 107 of time-driven loop 120 can determine hn+1, where h is the delta time period (i.e. the granularity that is governed by maximum local truncation error or voltage changes andtn+1=tn+hn+1.
Using hn+1, step 108 then predicts the next vector Vn+1 using extrapolation of previous steps and outputs simulation results of current step and, after additional units are simulated at time t, returns to step 101. Thus, time-driven loop 120 can perform transient analysis of the integrated circuit design over the specified time period T.
Note that the Jacobian matrix G is usually a sparse matrix and is determined by the circuit topology. If the circuit consists of only linear devices, e.g. resistors, then the fill-ins of the Jacobian matrix G are all constant numbers, and the vector V can be calculated through Gaussian elimination or LU decomposition method. However, most commercial application circuits include non-linear devices, e.g. diodes, MOSFETs, and/or bipolar junction transistors. In this case, the Jacobian matrix G becomes a function of the state vector V.
The dimension of the Jacobian matrix G is proportional to the size of the circuit. For state of art circuits that have millions of devices, the Jacobian matrix G is usually too big to be handled efficiently. In one embodiment, to more efficiently deal with such circuits, SPICE-like or Fast-SPICE algorithms can be used to partition the circuit into smaller blocks (generically called units above). This partitioning can be performed at the ideal source nodes and/or at weak coupling nodes, such as at the gates of transistors. Additionally, simplified models can be adopted to model the coupling effects at the boundary of different blocks. These types of simulation enhancements can be incorporated into technique 100. Thus, in one embodiment, technique 100 can be applied to each block of the integrated circuit design individually and asynchronously using loop 120. Such simulation enhancements can achieve 10-1000 times performance improvement with a reasonable sacrifice of accuracy.
Notably, for many blocks, loop 110 can converge (step 104) when k=1. In those cases, the first performance of step 102 solves the equation, while the second performance of step 102 effectively verifies the convergence. Thus, Newton-Raphson iteration does not significantly change the simulation result for many blocks. As a result, several known Fast-SPICE simulators turn off Newton-Raphson iteration by eliminating step 103, 104, and 106 such that step 105 directly follows step 102, to save the computation cost of additional iterations and accelerate the simulation speed.
This default elimination of the Newton-Raphson iteration from technique 100 usually works because most devices behave like linear devices from the simulator's point of view. However, as the scale of devices shrinks below 90 nm and the working voltage drops near the threshold voltage, the accuracy of technique 100 without Newton-Raphson iterations can deteriorate or even generate wrong simulation results. Therefore, a need arises for a simulation technique that selectively uses Newton-Raphson iterations.